The present invention relates to a method of manufacturing semiconductor devices, and is particularly useful in manufacturing high density semiconductor devices with submicron design features and active regions isolated by shallow, insulated trenches. The invention is particularly applicable in manufacturing semiconductor devices having features in the deep submicron range with reduced critical dimension.
Conventional semiconductor devices comprise a substrate having various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, forming the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and an oxide liner is thermally grown on the trench walls. The trench is then filled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active regions typically comprise source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each circuit component.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate, and depositing a nitride, e.g., silicon nitride, polish stop layer thereon. A photoresist mask is then applied to the nitride layer, and a pattern defining the trench areas is formed in the photoresist mask. This is accomplished by a photolithographic process in which selected areas of the photoresist are exposed to light and thereafter developed to form apertures extending to and exposing portions of the underlying nitride layer. The exposed portions of the nitride layer are etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped from the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control silicon-silicon oxide interface quality. The trench is then filled with an insulating material (or xe2x80x9ctrench fillxe2x80x9d), such as silicon dioxide derived from tetraethylorthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP) using the nitride layer as a polish stop, and the remaining nitride and pad oxide are stripped off from the active areas to complete the trench isolation structure.
As used herein, the term xe2x80x9ccritical dimensionxe2x80x9d or xe2x80x9cCDxe2x80x9d means the smallest permissible distance between two adjacent apertures on a photoresist mask. Since the features on the semiconductor device are formed by etching through the photoresist apertures and the nitride layer, CD also refers to the smallest permissible distance between such features. The critical dimension is a function of the precision in manufacturing the semiconductor device. The less control over aperture dimension in the photoresist, the greater the CD needed to prevent defects in the subsequently etched features on the semiconductor device.
The photoresist mask requires printing dense and isolated resist islands, as well as 0.25 micron or smaller isolated spaces and isolated lines on the silicon nitride layer, which is typically transparent Si3N4. The transparency of Si3N4 is problematic as light penetrating through the nitride layer during the lithographic process is reflected back at various angles to the photoresist layer. This increases the area of the photoresist exposed to light, resulting in a larger exposed area on the nitride layer after the photoresist is developed. Normally, the exposure level can be adjusted to account for a constant reflectivity level from the nitride layer. However, due to its refractive index mismatch with the photoresist and the silicon wafer substrate, the nitride layer thickness has a large effect on the reflectivity of the substrate. Thus, small thickness variations in the nitride layer result in a large xe2x80x9cswing effectxe2x80x9d, defined as the change in critical dimension (CD) as a function of nitride layer thickness. This is illustrated by FIGS. 1 and 2. FIG. 1 shows the calculated reflectivity of the Si3N4 substrate versus Si3N4 thickness. FIG. 2 shows the measured swing effect (both reflectivity and CD) on a 1500 xc3x85 thick Si3N4 film. Due to this large reflectivity and CD swing effect, the normal small variations in resist thickness that occur in manufacturing give rise to large, unpredictable changes in source/drain mass (SDM) CD.
These changes in CD are illustrated in FIGS. 3-6. As shown in FIG. 3, the silicon substrate 10 is provided with a nitride layer 12 by deposition in a furnace. A photoresist layer 14 is applied over the nitride layer 12 via spin coat or other process. The photoresist layer is then exposed with a stepper via a reticle field or mask and then developed to form a pattern represented by apertures 16, 18, and 20. The nitride layer is then etched to form apertures 22, 24, and 26, followed by etching of the silicon layer 10 to form trenches 28, 30, and 32, which are then filled with an oxide 34. The excess oxide is then removed via planarization, with the nitride layer 12 acting as a polish stop.
As shown in FIGS. 3-5, the nitride layer 12 does not have a uniform thickness. During the lithographic process, in which the photoresist is exposed to light to form the trench pattern, some of the light penetrates to and through the nitride layer and is reflected back. The greater the thickness of the nitride layer, the greater the amount of reflectivity, and the greater the exposed area of the photoresist for a given exposure by the reticle. Due to the nonuniformity of the nitride layer, the correct exposure level to obtain a specified CD will vary at different locations on the photoresist, and hence a constant exposure level will produce large variations in the width of the trenches, which can lead to bridging.
One approach to the problem of CD variation has been the use of organic bottom anti-reflective coatings (organic BARCs). However, the use of organic BARCs creates other problems, for example, higher level of defects, nonconformal coating over topography, and increased dense-to-isolated and line/space bias due to the BARC etching process. Moreover, the application of organic BARCs requires an extra step to apply the coating.
There is accordingly a need in the art for a method for providing a STI mask which will result in a more uniform trench dimension and hence will provide a critical dimension of less than 0.25 microns.
An advantage of the present invention is a method for manufacturing a semiconductor device which allows more concise control of critical dimension. Another advantage of the present invention is a method for manufacturing a semiconductor device, as above, which will allow a critical dimension of 0.25 microns or less. Yet another advantage of the present invention is a method of manufacturing a semiconductor device, as above, which does not require the application of additional layers to the wafer.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method for reducing critical dimension variation in a photoresist layer contained in a semiconductor composite. The composite includes a silicon nitride layer formed on a major surface of a silicon wafer, and a photoresist layer formed on the silicon nitride layer. The method provides for selection of an exposure level for the lithographic process for exposing a portion of the composite, the level of exposure being selected based on the reflectance of the silicon nitride layer in the particular portion. The photoresist layer in the portion is then exposed at the selected exposure level in accordance with a pattern, thereby forming at least one exposed area and at least one unexposed area. This process is repeated for different portions of the composite having different nitride layer thickness, and for each portion, a different lithographic exposure level may be selected based on the calculated or measured reflectivity of the nitride layer in that portion.
After the entire composite has been exposed, it is developed to form apertures in the photoresist having a substantially uniform critical dimension across the entire photoresist. The nitride layer and the silicon wafer are then etched in well-known manner, the low CD of the photoresist carrying through to formation of the STI structure in the silicon wafer substrate.